Each ADC module has a hardware sample averaging circuit that can be used to generate higher precision results. An averaging circuit can be used to accumulate up to 64 samples and average them to form a single data entry to appear in the sequencer FIFO. By default, the hardware sample averaging circuit is off and all the data from the converter passes through the sequencer FIFO. All channels are averaged equally irrespective of their configuration (single ended or differential). It is important to understand that throughput is decreased proportionally to the number of samples in the averaging calculation.