The ADC module is clock gated, e.g., before the ADC module can be used, the clock to the ADC module must be enabled by setting Rx bit in the Run mode clock gating register. The ADC control logic runs at 16 MHz. The clock source can be selected by setting the clock source bit in the ADC clock source register. The clock source can be thePLL or precision internal oscillator, otherwise, the system clock must be at least 16 MHz. To reduce the overall current consumption, the ADC can operate in deep sleep mode with precision internal oscillator selected as the clock source.